1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a multi-level interconnect technology.
2. Description of the Related Art
In general, a contact for electrically connecting upper and lower conductive layers is formed as follows in a semiconductor device. After an interlayer dielectric film is formed on the lower conductive layer, a contact hole to expose the lower conductive layer is formed by etching the interlayer dielectric film in which the contact is to be made. The upper conductive layer is formed by depositing a conductive material in the contact hole and on the interlayer dielectric film so as to fill the contact hole, and patterning the conductive material on the interlayer dielectric film to have a desired shape. When the aspect ratio of the contact hole is large or a material for filling the contact hole is different from the material of which the upper conductive layer is formed, the patterned conductive material is not used as the upper conductive layer. In other words, the conductive material deposited on the interlayer dielectric film is removed and the conductive material is left only inside the contact hole. What fills the contact hole is called a contact plug. In the present invention, the contact plug is formed of polysilicon, which is widely used for semiconductor devices.
When the contact plug is formed of polysilicon, the conductive material deposited on the interlayer dielectric film must be removed. Typically, the conductive material is removed by a chemical mechanical polishing (CMP) method and an etch-back method. The CMP method is, however, costly and its process stability has not been sufficiently secured yet. Thus the CMP method often causes several problems for the mass production of semiconductor devices. Also, in the CMP method, thickness uniformity deteriorates since the abrasion rate varies depending on the surface area of the wafer. On the other hand, the etch back method is less costly. However, thickness uniformity also deteriorates since the etch rate varies depending on the size of the contact hole.
In particular, referring to FIG. 1 showing a polysilicon contact plug formed using the conventional etch-back method, an interlayer dielectric film 13, which is typically formed of a silicon oxide layer, with a contact hole opened therein, is formed on a lower conductive layer 11 on a substrate. A polysilicon contact plug 15 is formed inside the contact hole. As shown in FIG. 1, the contact plug 15 is slightly recessed, and thus it is not flush with the interlayer dielectric film 13. This is because the polysilicon filling the contact hole is etched and recessed during over-etching of polysilicon using a gas mixture obtained by mixing HBr or He with Cl.sub.2 or SF.sub.6 so that the polysilicon is not left on the interlayer dielectric film 13. The degree of the recession of the contact plug 15 is larger when the uniformity of the etch rate deteriorates due to the large-size contact hole.
The recessed polysilicon contact plug 15, shown in FIG. 1, can cause various problems in subsequent processing steps. In particular, one such problem is observed especially when there is a pattern misalignment as illustrated in FIG. 2. In detail, an etch stop layer 17 is formed on the contact plug 15 and the interlayer dielectric film 13 as shown in FIG. 1. The etch stop layer 17 is usually formed of a silicon nitride layer when the interlayer dielectric film 13 is a silicon oxide layer and has a high etch selectivity with respect to the interlayer dielectric film 13. Next, A second interlayer dielectric film 19 is formed on the etch stop layer 17. Then a second contact hole 20 exposing the contact plug 15 is formed in the second interlayer dielectric film 19. If there is a misalignment between the second contact hole 20 and the underlying plug 15 as shown in FIG. 2, a spacer A of the silicon nitride layer 17 can be formed at the edge of the interlayer dielectric film 13. Accordingly, the contact resistance of the completed contact increases or, in worst case, the contact plug 15 does not get completely exposed. Therefore, contact failure can occur.
Also, when the contact plug 15 is recessed, the degree of planarization of the second dielectric layer 19 overlying the contact plug 15 gets worse. Therefore, it is difficult to accurately pattern the dielectric layer overlying the contact plug 15.